Entity Inport is Port( DB: inout std_logic_vector(7 downto 0); IP : in std_logic_vector(7 downto 0); CS : in std_logic; RD : in Std_logic); end Inport; Architecture A_Inport of Inport is signal T : std_logic; Begin
DB
end A_Inport;
Entity Outport is Port( DB: inout std_logic_vector(7 downto 0); OP : out std_logic_vector(7 downto 0); CS : in std_logic; WR : in Std_logic); end Outport; Architecture A_Outport of Outport is
Begin Process (WR) Begin if WR'event and WR='1' then if CS='1' then OP end if; end if; end Process; end A_Outport;
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